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EM250
SC2_SPICFG [0x442C]
15
0-R
0
0
0-R
7
14
0-R
0
0
0-R
6
13
0-R
0
SC_SPIRXDRV
0-RW
5
12
0-R
0
SC_SPIMST
0-RW
4
11
0-R
0
SC_SPIRPT
0-RW
3
10
0-R
0
SC_SPIORD
0-RW
2
9
0-R
0
SC_SPIPHA
0-RW
1
8
0-R
0
SC_SPIPOL
0-RW
0
NOTE: Changing the SC2_SPICFG register is only allowed when the serial controller is
disabled, when SC2_MODE is 0.
SC_SPIRXDRV
SC_SPIMST
SC_SPIRPT
SC_SPIORD
SC_SPIPHA
SC_SPIPOL
[5]
[4]
[3]
[2]
[1]
[0]
Receiver-driven mode selection bit (SPI master mode only). Clearing this bit will initiate
transactions when transmit data is available. Setting this bit will initiate transactions when
the receive buffer (FIFO or DMA) has space.
Setting this bit will put the SPI in master mode while clearing this bit will put the SPI in
slave mode.
This bit controls behavior on a transmit buffer underrun condition in slave mode. Clearing
this bit will send the BUSY token (0xFF) and setting this bit will repeat the last byte.
Changing this bit will only take effect when the transmit FIFO is empty and the transmit
serializer is idle.
Clearing this bit will result in the Most Significant Bit being transmitted first while setting
this bit will result in the Least Significant Bit being transmitted first.
Clock phase configuration is selected with clearing this bit for sampling on the leading (first
edge) and setting this bit for sampling on second edge.
Clock polarity configuration is selected with clearing this bit for a rising leading edge and
setting this bit for a falling leading edge.
SC2_SPISTAT [0x4420]
15
0-R
0
0
0-R
7
14
0-R
0
0
0-R
6
13
0-R
0
0
0-R
5
12
0-R
0
0
0-R
4
11
0-R
0
SC_SPITXIDLE
0-R
3
10
0-R
0
SC_SPITXFREE
0-R
2
9
0-R
0
SC_SPIRXVAL
0-R
1
8
0-R
0
SC_SPIRXOVF
0-R
0
SC_SPITXIDLE
SC_SPITXFREE
SC_SPIRXVAL
SC_SPIRXOVF
120-0082-000V Rev 1.1
[3]
[2]
[1]
[0]
This bit is set when the transmit FIFO is empty and the transmitter is idle.
This bit is set when the transmit FIFO is ready to accept at least one byte.
This bit is set when the receive FIFO contains at least one byte.
This bit is set when the receive FIFO has been overrun. This bit clears when the data
register ( SC2_DATA ) is read.
Page 70
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